FPGA Reconfigurable Computing Research Engineer – Job Order 2662

near Seven Corners, VA 22044
US citizens and Permanent Residents only
Compensation: $90K to $150K, possibly more
Relocation allowance is available
Recent Phd’s to 10+ years of experience


My client seeks talented researchers to lead and impact state-of-the-art research and development in the area of reconfigurable computing. This group is a pioneer of research related to field programmable gate arrays (FPGAs) including architecture, tools, applications, hardware trust, and security. It works closely with leading agencies such as DARPA, IARPA, and NASA where reconfigurable computing is a critical technology. Spanning the days of homogeneous logic devices to today’s billion transistor system on a chip devices, RCG has led the way from being the first to implement application-level partial runtime reconfiguration, investigating 3D FPGA architectures, developing autonomous system on chip architectures, releasing open source CAD tools that target real physical devices, and IP to address software/hardware co-design complexity.

Today, this group is addressing our nation’s challenges in big data, hardware cybersecurity, trusted systems, cognitive radio and more. This position will lead the research and technical direction of FPGA CAD tools. Architect and lead the development of complex CAD tools which support highly specialized domains. Perform research on ground breaking CAD solutions, including integration with higher level hardware/software co-design and HLS solutions. Realize effectiveness of solutions on physical FPGAs and custom ASIC fabrication. Lead research, propose major innovations, collaborate with peers within the group and across ISI, publish results in top tier conferences, and contribute to or lead proposals.

Preferred Qualifications:

PhD or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science with experience in Verilog/VHDL/C programming for FPGAs.

Five years of strong C++ development experience, including demonstrable contributions to large-scale C++ projects. Commercial or open-source development experience a plus.

Five years of experience designing, developing, implementing, and debugging firmware for FPGAs, including Xilinx Virtex6 or later architectures. Altera also desirable.

Solid understanding of CAD algorithms, including synthesis, partitioning, mapping, placing, and routing.

Experience implementing at least one of the above CAD algorithms in software.

Expert level use of Xilinx or Altera implementation tools.

Detailed understanding of mapped and unmapped netlist formats, such as EDIF, XDL, and structural Verilog.

Proficiency in software cross-compiling and cross-debugging.

Proficiency in hardware development in VHDL or Verilog, or SystemC or SystemVerilog.

Experience with Torc, ABC, VPR, VTR, RapidSmith, GoAhead, or similar commercial tools a plus.
Experience in device level reliability, fault tolerance, or security a plus.

Previous publications, patents, or innovations related to FPGA CAD or EDA algorithms and tools.
Experience leading or contributing to proposals a significant plus.

Applicants selected for this position will require access to ITAR materials. According to U.S. government regulations, ONLY U.S. citizens OR lawful permanent residents (green card) are eligible for ITAR access.

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