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ASIC / FPGA EDA Computer Scientist – Job Order 3194

ASIC / FPGA EDA Computer Scientist – Job Order 3194

Arlington, VA, Boston, MA or Los Angeles, CA
Compensation: up to $120K
0 – 10 years of experience
US citizens or permanent resident

My client, a technology research organization, is looking for highly talented, motivated researchers to lead and impact state of the art research and development in the area of reconfigurable computing. This position will lead research in algorithm development for custom internal tools which target FPGA and ASIC front end design. These tools solve challenging problems in hardware security, high level abstraction for hardware design, and machine learning acceleration for critical systems. Realize effectiveness of solutions on physical FPGAs and custom ASIC fabrication. Lead research, propose major innovations, collaborate with peers within the group and across the company, publish results in top tier conferences, and contribute to or lead proposals.

We are looking for highly talented, motivated developers to perform research and development in the area of digital design and CAD tools for ASIC and FPGA hardware. This position will collaborate with a high caliber team to research and develop cutting edge solutions in reconfigurable architectures, design tools, and hardware security. Be an active member of a fast-paced Front-end Research and Development team supporting architecture definition, custom EDA tool development and realization on ASICs and FPGAs. This position will lead research, propose major innovations, collaborate with peers within the group and across the organization, publish results in top tier conferences, and contribute to or lead proposals.

Position specific JOB QUALIFICATIONS:

PhD or MS and equivalent experience in Computer Engineering, Electrical Engineering, or Computer Science required.
Previous publications/patents, or innovations related to CAD tool development, test and verification, computer architecture, or hardware machine learning.
Solid understanding of CAD algorithms leveraging High-Level Languages, LLVM, or High-Level Synthesis.
Experience with standard digital design tools (FPGAs and ASIC) such as Xilinx Vivado, Intel Quartus, Synopsys Design Compiler, , Cadence Stratus, or Open Source CAD tools. .
Ability to handle Controlled Unclassified Information (CUI). Per U.S. government regulations, eligibility to handle CUI requires U.S. Citizenship.
Preferred Job Qualifications:

1-3 years of experiences developing and/or verifying embedded systems with FPGAs or custom ASICs.
1-3 years of experience using digital logic verification and/or model checking tools such as Synopsys Formality or Cadence Conformal.
Understanding of Machine Learning toolkits (Keras/TensorFlow/PyTorch)..
The University of Southern California values diversity and is committed to equal opportunity in employment.

To apply for this job email your details to paulreino@accuritstaffing.com

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