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ASIC / FPGA Research Engineer – Job Order 3190

ASIC / FPGA Research Engineer – Job Order 3190

Arlington, VA, Boston, MA or Los Angeles, CA
Compensation: up to $120K
0 – 10 years of experience
US citizens or permanent resident

My client, a technology research organization, is looking for highly talented, motivated researchers to lead and impact state of the art research and development in the area of reconfigurable computing. This position will lead research in algorithm development for custom internal tools which target FPGA and ASIC front end design. These tools solve challenging problems in hardware security, high level abstraction for hardware design, and machine learning acceleration for critical systems. Realize effectiveness of solutions on physical FPGAs and custom ASIC fabrication. Lead research, propose major innovations, collaborate with peers within the group and across the company, publish results in top tier conferences, and contribute to or lead proposals.

Activities
Researching and developing toolsets to map AI algorithms directly to hardware,
Optimizing full scale testing of billion transistor FPGAs to minimal runtime,
Performing experiments on the International Space Station,
Utilizing chip design tools to fabricate novel computer architectures.

REQUIRED QUALIFICATIONS / EXPERIENCE

Knowledge of computer architecture, reconfigurable computing (FPGAs) and relevant programming languages (System Verilog, VHDL, C/C++, Python).

Experience with CAD algorithms and tools for ASIC or FPGAs, test and verification, hardware security, or hardware machine learning.

Prior experience with Digital Design and standard ASIC or FPGA tools (Synopsys Design Compiler, Cadence Stratus, Xilinx Vivado, Intel Quartus).

Proven leadership ability.

Excellent written and oral communication skills.

Ability to handle Controlled Unclassified Information (CUI). Per U.S. government regulations, eligibility to handle CUI requires U.S. Citizenship.

PREFERRED QUALIFICATIONS / EXPERIENCE

M.S. Degree in Electrical and Computer Engineering or equivalent.
Experience in digital logic verification and/or model checking tools such as Synopsys Formality or Cadence Conformal, a plus.
Previous patents, publications, or other demonstration of innovations in digital design, a plus.

To apply for this job email your details to paulreino@accuritstaffing.com

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