ASIC / FPGA Security Computer Scientist – Job Order 3193
Arlington, VA, Boston, MA or Los Angeles, CA
Compensation: up to $120K
0 – 10 years of experience
US citizens or permanent resident
My client, a technology research organization, is looking for highly talented, motivated researchers to lead and impact state of the art research and development in the area of reconfigurable computing. This position will lead research in algorithm development for custom internal tools which target FPGA and ASIC front end design. These tools solve challenging problems in hardware security, high level abstraction for hardware design, and machine learning acceleration for critical systems. Realize effectiveness of solutions on physical FPGAs and custom ASIC fabrication. Lead research, propose major innovations, collaborate with peers within the group and across the company, publish results in top tier conferences, and contribute to or lead proposals.
We are looking for highly talented, motivated researchers to lead research and development in the area of secure hardware.
Research and develop techniques to quantifiably measure the effectiveness and vulnerabilities of hardware security approaches.
Lead efforts analyzing and evaluating the effectiveness of hardware security techniques such as obfuscation, logic locking, or programmability for use in advanced lithography nodes and real-world System on a Chip use cases in terms of quantifiable security, overhead, and useability metrics.
This position will lead research, propose major innovations, collaborate with peers within the group and across the organization, publish results in top tier conferences, and contribute to or lead proposals.
Position specific JOB QUALIFICATIONS:
PhD or MS and equivalent experience in Computer Engineering, Electrical Engineering, or Computer Science required.
Established publication record in Hardware Security, Computer Architecture, or ASIC design.
Strong software engineering skills (Algorithms, Data Structures, etc)
Expert level programming in Verilog or VHDL.
Experience scripting standard digital design tools such as Cadence Genus, and Innovus or Synopsys Design Compiler, and IC compiler.
Expert level understanding of SAT, ATPG, or reverse engineering tools.
Ability to evaluate, critique, adapt, and apply published research on hardware security and ASIC design.
Ability to handle Controlled Unclassified Information (CUI). Eligibility to handle CUI requires U.S. Citizenship.
Preferred Job Qualifications:
Publication on or experience with circuit obfuscation, logic locking, IP redaction, side channels, and associated vulnerabilities a strong plus.
Familiarity with 3rd generation Artificial Intelligence a plus.
Experience with open source CAD tools such as ABC, Yosys, etc a plus.
To apply for this job email your details to email@example.com