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Computer Scientist, Digital Design and Security, – Job Order 3071

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Computer Scientist, Digital Design and Security, remote- Job Order 3071

near Seven Corners, VA 22044
US citizens or permanent resident only
Compensation: $100K to $150K
Relocation allowance is available
Remote work during and maybe after COVID

My client, a technology research organization, is looking for highly talented, motivated researchers to lead and impact state of the art research and development in the area of reconfigurable computing. This position will lead research in algorithm development for custom internal tools which target FPGA and ASIC front end design. These tools solve challenging problems in hardware security, high level abstraction for hardware design, and machine learning acceleration for critical systems. Realize effectiveness of solutions on physical FPGAs and custom ASIC fabrication. Lead research, propose major innovations, collaborate with peers within the group and across the company, publish results in top tier conferences, and contribute to or lead proposals.

The Reconfigurable Computing Group (RCG) is a leader in disrupting and advancing the fields of front-end ASIC and FPGA design, computer architecture, and EDA tools. As an applied research lab, our work spans the creation and maturation of ideas from academic conception to applied research prototypes.

The Reconfigurable Computing Group (RCG) is a leader in disrupting and advancing the fields of front-end ASIC and FPGA design, computer architecture, and EDA tools. As an applied research lab, our work spans the creation and maturation of ideas from academic conception to applied research prototypes.

RCG staff can be found:

Researching and developing toolsets to map AI algorithms directly to hardware,
Optimizing full scale testing of billion transistor FPGAs to minimal runtime,
Performing experiments on the International Space Station,
Utilizing their MOSIS service to fabricate novel computer architectures.
Our success is based on investing in our staff through a culture centered on:

Learning and idea generation,
Transparent and constructive feedback, and
Continual growth through contributing to, creating, and leading a research agenda.
We are looking for highly talented, motivated researchers to lead research and development in the area of secure hardware. Be a member of a high caliber team creating the world’s first customized accelerator for native Fully Homomorphic Encryption (FHE). Lead the synthesis and floorplanning of complex FHE architectures utilizing custom EDA tools. Be an active member of fast-paced ASIC Development team supporting the full life cycle from functional architecture definition to physical implementation, verification, and tape-out. Support efforts analyzing and evaluating the effectiveness of hardware security techniques such as obfuscation, logic locking, or programmability for use in advanced lithography nodes and real-world System on a Chip use cases in terms of quantifiable security, overhead, and usability metrics. Lead development while contributing to advanced research, collaborating with peers within the group and across the organization, and contributing to publications in top tier conferences.

JOB QUALIFICATIONS:

PhD or MS and equivalent experience in Computer Engineering, Electrical Engineering, or Computer Science required.
Previous publications, patents, or innovations related to EDA for digital design, hardware security, formal verification, or novel application mapping.
Expert-level understanding of FPGA devices and architectures such as Xilinx Virtex-7, UltraScale, and UltraScale+.
Five years of digital design experience using Xilinx Vivado or Intel Quartus CAD tools and commercial/academic cad flows.
Five years of C++/Java and Python development experience, including contributions to large-scale commercial or open-source software projects.
Ability to evaluate, apply, and mature published research to real-world problems at scale on prototype systems.
Qualified candidates for this position must be willing and eligible to apply for and maintain a collateral Secret clearance. Per U.S. government regulations, eligibility for this clearance requires U.S. citizenship. Current SECRET clearance or higher is a plus.

Preferred Job Qualifications:

Understanding of FPGA bitstream formats and experience using tools such as Google Project X-Ray, RapidWright, or TORC to develop custom bitstreams.
3-5 years of experiences developing and/or verifying wireless or digital signals processing systems.
3-5 years of experience using digital logic formal verification and/or model checking tools such as Synopsys Formality, Cadence Conformal, Synopsys VC Formal
The University of Southern California values diversity and is committed to equal opportunity in employment.

Minimum Education: Master’s degree, Combined experience/education as substitute for minimum education Minimum Experience: 3 years Minimum Field of Expertise: Knowledge of research processes and computer science.

To apply for this job email your details to paulreino@accuritstaffing.com

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