Reconfigurable Computing Research Scientist – Job Order 3054
near Seven Corners, VA 22044
US citizens and Permanent Residents only
Compensation: $90K to $150K, possibly more
Relocation allowance is available
Recent PhD’s to 3+ years of experience
My client, a technology research organization, is looking for highly talented, motivated researchers to lead and impact state of the art research and development in the area of reconfigurable computing. This position will lead research in algorithm development for custom internal tools which target FPGA and ASIC front end design. These tools solve challenging problems in hardware security, high level abstraction for hardware design, and machine learning acceleration for critical systems. Realize effectiveness of solutions on physical FPGAs and custom ASIC fabrication. Lead research, propose major innovations, collaborate with peers within the group and across the company, publish results in top tier conferences, and contribute to or lead proposals.
Applicants selected for this position will require access to ITAR materials. According to U.S. government regulations, ONLY U.S. citizens OR lawful permanent residents (green card) are eligible for ITAR access.
PhD in Computer Engineering, Electrical Engineering, or Computer Science required.
Experience with Machine Learning and/or Graph partitioning algorithms targeting FPGAs or ASICs.
Experience designing, developing, implementing, and debugging firmware for FPGAs, including Xilinx Virtex7 or later architectures. Experience with Intel Aria-10 and Stratix-10 devices also desirable.
C++/Java and Python development experience, including contributions to large-scale software projects, commercial or open-source.
Solid understanding of CAD algorithms including synthesis, partitioning, mapping, placing, and routing.
Expert level use of Xilinx or Intel FPGA implementation tools, including High level synthesis.
Previous publications, patents, or innovations related to FPGA productivity, CAD or EDA algorithms and tools.
Detailed understanding of mapped and unmapped netlist formats, such as EDIF, XDL, and structural Verilog.
Proficiency in software cross-compiling and cross-debugging
Experience with Torc, ABC, VPR, VTR, RapidSmith, GoAhead, or similar tools a plus.
Experience with Amazon EC2 F1 instances or related FPGA-based cloud platforms.
Experience with multi-processor system-on-chip, embedded systems software (Linux, cross-compilers) and Python productivity for FPGAs (i.e. Pynq).
Experience leading or contributing to proposals a significant plus.
The University of Southern California values diversity and is committed to equal opportunity in employment.
Minimum Education: Master’s degree, Combined experience/education as substitute for minimum education
Minimum Experience: 3 years
Minimum Field of Expertise: Knowledge of research processes and computer science.
To apply for this job email your details to firstname.lastname@example.org