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Research Programmer II, EDA Developer, remote – Job Order 3073

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Research Programmer II, EDA Developer, remote – Job Order 3073

near Seven Corners, VA 22044
US citizens or permanent resident only
Compensation: $100K to $150K
Relocation allowance is available
Remote work during and maybe after COVID

My client, a technology research organization, is looking for highly talented, motivated researchers to lead and impact state of the art research and development in the area of reconfigurable computing. This position will lead research in algorithm development for custom internal tools which target FPGA and ASIC front end design. These tools solve challenging problems in hardware security, high level abstraction for hardware design, and machine learning acceleration for critical systems. Realize effectiveness of solutions on physical FPGAs and custom ASIC fabrication. Lead research, propose major innovations, collaborate with peers within the group and across the company, publish results in top tier conferences, and contribute to or lead proposals.

The Reconfigurable Computing Group (RCG) is a leader in disrupting and advancing the fields of front-end ASIC and FPGA design, computer architecture, and EDA tools. As an applied research lab, our work spans the creation and maturation of ideas from academic conception to applied research prototypes.

The Reconfigurable Computing Group (RCG) is a leader in disrupting and advancing the fields of front-end ASIC and FPGA design, computer architecture, and EDA tools. As an applied research lab, our work spans the creation and maturation of ideas from academic conception to applied research prototypes.

RCG staff can be found:

Researching and developing toolsets to map AI algorithms directly to hardware,
Optimizing full scale testing of billion transistor FPGAs to minimal runtime,
Performing experiments on the International Space Station,
Utilizing their MOSIS service to fabricate novel computer architectures.
Our success is based on investing in our staff through a culture centered on:

Learning and idea generation,
Transparent and constructive feedback, and
Continual growth through contributing to, creating, and leading a research agenda.
We are looking for highly talented, motivated researchers to lead research and development in the area of secure hardware. Be a member of a high caliber team creating the world’s first customized accelerator for native Fully Homomorphic Encryption (FHE). Lead the synthesis and floorplanning of complex FHE architectures utilizing custom EDA tools. Be an active member of fast-paced ASIC Development team supporting the full life cycle from functional architecture definition to physical implementation, verification, and tape-out. Support efforts analyzing and evaluating the effectiveness of hardware security techniques such as obfuscation, logic locking, or programmability for use in advanced lithography nodes and real-world System on a Chip use cases in terms of quantifiable security, overhead, and useability metrics. Lead development while contributing to advanced research, collaborating with peers within the group and across the organization, and contributing to publications in top tier conferences.

Qualifications
Graduate degree or equivalent experience in Computer Engineering, Electrical Engineering, or Computer Science required.
Five years of digital design experience for ASIC or FPGAs using Synopsys, Cadence, Xilinx or Intel CAD tools and commercial/academic cad flows.
3-5 years development experience (C++/Python) including demonstrable contributions to large-scale projects (commercial or open-source development).
3-5 years of Embedded systems development, including Linux kernel development, device drivers, cross-compilers, memory subsystems, and data transfer protocols.
Solid understanding of CAD algorithms leveraging High-Level Languages, LLVM, and High-Level Synthesis targeting heterogenous hardware platforms to accelerate end-user development.
Strong experience with embedded systems hardware/software co-design and design space exploration with heterogenous computing architectures.
Experienced user of standard digital design tools such as Cadence Stratus, Genus, and Innovus or Synopsys Synphony, Design Compiler, and IC compiler.
Ability to evaluate, apply, and mature published research to real-world problems at scale on prototype systems.
Ability to handle Controlled Unclassified Information (CUI). Per U.S. government regulations, eligibility to handle CUI requires U.S. Citizenship

Preferred Job Qualifications:

3-5 years of experiences developing and/or verifying embedded systems with custom ASIC or FPGAs.
3-5 years of experience using digital logic formal verification and/or model checking tools such as Synopsys Formality, Cadence Conformal, Synopsys VC Formal.
Experience targeting 12nm or smaller fabrication nodes a significant plus.
Understanding of Machine Learning toolkits (Keras/TensorFlow/PyTorch) with demonstrable contributions to their application across heterogeneous hardware systems, including training and inference.
Previous publications, patents, or innovations related to CAD tool development, Homomorphic Encryption, Machine Learning, FPGA security, or FPGA architecture.
Experience with software revision control systems such as Git, Mercurial, SVN, etc.

Minimum Education: Master’s degree, Combined work experience and education as equivalent Minimum Experience: 3 years Minimum Field of Expertise: Relevant work experience to provide strong technical knowledge of programming and analysis as well as senior or lead experience. Demonstrated ability to stand in for researchers as circumstances require. Demonstrated creativity and innovation in solving conceptual programming problems.

 

To apply for this job email your details to paulreino@accuritstaffing.com

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