Principal Hardware Architect, Secure Digital Systems – Job Order 3505

Principal Hardware Architect, Secure Digital Systems – Job Order 3505

Somerville, MA
$150K to $190K
Top Benefits plus 10% 401K contribution
Must be a U.S. Citizen and eligible for security clearance
Relocation assistance is available

Overview
My client is seeking a seasoned digital hardware architect with deep expertise in secure system design using ASIC and FPGA technologies. This role involves shaping the architecture and guiding the implementation of cryptographic hardware solutions that meet stringent security standards.

Role Summary
The selected candidate will lead the design and specification of secure digital logic systems, translating high-level security requirements into optimized hardware implementations. You’ll collaborate across front-end and back-end engineering teams to ensure robust, tamper-resistant designs, and interface with system engineers to support documentation, testing, and integration efforts.

Core Competencies
Candidates should bring strong familiarity with hardware-based cryptographic mechanisms and secure design principles, including:
– Public-key algorithms (e.g., RSA, ECC)
– Symmetric encryption standards (e.g., AES, MACs, block cipher modes)
– Protocols for secure communication (e.g., key exchange, digital signatures, key wrapping)
– Hardware isolation techniques (e.g., secure enclaves, memory partitioning)
– Embedded security protocols (e.g., secure boot, attestation, MFA, certificate handling)

Technical Expertise
– Deep understanding of digital logic design and computer architecture
– Proficiency in HDL languages (SystemVerilog, Verilog, VHDL)
– Ability to convert system-level requirements into actionable design specs for RTL and physical implementation teams
– Experience optimizing for performance, power efficiency, and silicon area
– Familiarity with transistor-level simulation and parasitic-aware layout workflows

Responsibilities
– Architect and simulate secure digital circuits
– Contribute to holistic system design and integration
– Evaluate algorithmic feasibility for hardware acceleration
– Lead development of complex chip-level designs
– Navigate ambiguous or evolving customer requirements with clarity and initiative
– Mentor junior engineers and codify best practices
– Support proposal development and technical outreach
– Oversee layout planning and verification processes
– Execute additional engineering tasks as needed

Skills & Attributes
– Strong grasp of IC design fundamentals and semiconductor behavior
– Ability to produce comprehensive design documentation
– Capable of leading small technical teams
– Exceptional communication and analytical skills
– Meticulous attention to detail and time management
– Proven ability to prioritize and deliver under deadlines

Qualifications
Education:
– Bachelor’s degree in Electrical Engineering or related discipline required
– Master’s degree preferred

Experience:
– 5–7 years with a bachelor’s, 3–5 years with a master’s, or 0–2 years with a PhD in ASIC/FPGA hardware design

Bonus Expertise
– Post-quantum cryptographic algorithms
– Side-channel resistance techniques
– Lightweight cryptographic primitives
– Secure key storage technologies
– Hardware entropy sources (TRNGs, PUFs)
– Anti-tamper and electromagnetic shielding (TEMPEST)
– Mathematical foundations: modular arithmetic, finite fields, coding theory
– Familiarity with NSA/NIST certification processes

Candidates must be eligible to obtain and maintain a U.S. government security clearance.